Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible and easily configurable, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use cases.
The emergence of Deep Learning as an omnipresent workload has driven FPGA architecture evolution as well. Academic researchers have proposed optimizing the architecture of FPGAs to better fit the needs of DL workloads and FPGA companies now have AI-optimized FPGAs in their product portfolios.
FPGAs are very well-suited for prototyping and accelerating the rapidly changing algorithms and novel network architectures in the field of DL. In addition, DL is being used to assist in chip design processes such as power prediction, floorplanning, etc. including for FPGAs.
In this webinar, we will discuss recent innovations in DL-optimized FPGA architecture, using AI to estimate things such as power consumption on (new or existing) FPGAs and new types of neural network accelerators using existing FPGAs.